Texas Instruments MSP430x1xx - Manual (Page 207)

Timer_B Registers
11-31
Timer_B
Bit 10: Unused
Bits 11, 12: Configure 16-bit timer (TBR) for 8-bit, 10-bit, 12-bit, or 16-bit
operation
CNTL = 0: 16-bit length, TBR
(max)
is 0FFFFH
CNTL = 1: 12-bit length, TBR
(max)
is 0FFFH
CNTL = 2: 10-bit length, TBR
(max)
is 03FFH
CNTL = 3: 8-bit length, TBR
(max)
is 0FFH
Bits 13, 14: Load compare latches, individually or in groups. The load signal
is controlled via the CLLDx bits located in the appropriate
capture/compare control register CCTLx.
TBCLGRP = 0: load individually
Load of the shadow registers is defined in each
individual CCTLx register by bits CLLDx. The
CLLD bits in each CCTLx register define the
operating mode for the shadow registers.
TBCLGRP = 1: Three groups are selected (TBCL1 + TBCL2,
TBCL3 + TBCL4, TBCL5 + TBCL6):
TBCL1 + TBCL2: The CLLD bits in CCTL1
define the operating mode.
TBCL3 + TBCL4: The CLLD bits in CCTL3
define the operating mode.
TBCL5 + TBCL6: The CLLD bits in CCTL5
define the operating mode.
TBCLGRP = 2: Two groups are selected (TBCL1 + TBCL2 +
TBCL3, TBCL4 + TBCL5 + TBCL6):
TBCL1 + TBCL2 + TBCL3: The CLLD bits in
CCTL1 define the operating mode.
TBCL4 + TBCL5 + TBCL6: The CLLD bits in
CCTL4 define the operating mode.
TBCLGRP = 3: One group is selected (all TBCLx registers):
The CLLD bits in CCTL1 define the operating
mode for all shadow registers.
Bit 15: Unused