Texas Instruments MSP430x1xx - Manual (Page 46)

Operating Modes
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3.5 Operating Modes
The MSP430 family was developed for ultralow-power applications and uses
different levels of operating modes. The MSP430 operating modes, shown in
Figure 3–10, give advanced support to various requirements for ultralow
power and ultralow energy consumption. This support is combined with an
intelligent management of operations during the different module and CPU
states. An interrupt event wakes the system from each of the various operating
modes and the RETI instruction returns operation to the mode that was
selected before the interrupt event.
The ultra-low power system design which uses complementary metal-oxide
semiconductor (CMOS) technology, takes into account three different needs:
- The desire for speed and data throughput despite conflicting needs for
ultra-low power
- Minimization of individual current consumption
- Limitation of the activity state to the minimum required by the use of low
power modes
There are four bits that control the CPU and the main parts of the operation
of the system clock generator: CPUOff, OscOff, SCG0, and SCG1. These four
bits support discontinuous active mode (AM) requests, to limit the time period
of the full operating mode, and are located in the status register. The major
advantage of including the operating mode bits in the status register is that the
present state of the operating condition is saved onto the stack during an
interrupt service request. As long as the stored status register information is
not altered, the processor continues (after RETI) with the same operating
mode as before the interrupt event. Another program flow may be selected by
manipulating the data stored on the stack or the stack pointer. Being able to
access the stack and stack pointer with the instruction set allows the program
structures to be individually optimized, as illustrated in the following program
flow:
- Enter interrupt routine
The interrupt routine is entered and processed if an enabled interrupt awakens
the MSP430:
J The SR and PC are stored on the stack, with the content present at the
interrupt event.
J Subsequently, the operation mode control bits OscOff, SCG1, and
CPUOff are cleared automatically in the status register.