Texas Instruments MSP430x1xx - Manual (Page 161)

Timer Modes
10-21
Timer_A
10.5.2 Output Control Block
The output control block prepares the value of the OUTx signal, which is
latched into the OUTx flip-flop with the next positive timer clock edge, as shown
in Figure 10–23 and Table 10–2. The equal signals EQUx and EQU0 are
sampled during the negative level of the timer clock, as shown in Figure 10–23.
Figure 10–23. Output Control Block
The timer is Incremented with the rising edge of the timer clock.
Timer
Clock
Timer
TAR
EQUx
EQU0
EQU0, Delayed
Used in Up Mode Only
TAR = n
CCRx = n
n–2 n–1 n n+1 FFFF or CCR0 0 1
TAR = 0
or
TAR = CCR0
EQU0 delayed is used in up mode, not EQU0. EQU0 is active high when
TAR = CCR0. EQU0 delayed is active high when TAR = 0.
D Q
Reset
POR
OUTx
Set
Timer Clock
OUTx
OUTx Signal
EQU0
EQUx
OMx2 OMx1 OMx0
Output
Control
Block