Texas Instruments MSP430x1xx - Manual (Page 274)

Comparator_A Control Registers
14-8
The control bits CAPD.0 to CAPD.7 are initially reset, enabling all the input
buffers for the associated port. The port input buffer is disabled if the according
CAPD.x bit is set. See device data sheet for port associations.
The ability to disable the input buffer for the device pin applies to up to eight
inputs of the associated digital I/O port (check device data sheet for
implementation details). For example, the x11x1 devices have CA1
multiplexed on pin P2.4 and CA0 multiplexed on pin P2.3, so the
Comparator_A is associated with port P2. On this device, all input buffers
associated with all P2 pins (P2.x) may have the capability to be disabled with
the CAPD register.
7
rw-(0) rw-(0) rw-(0) rw-(0)
CAPD.3
rw-(0)
CAPD.2
rw-(0)
CAPD.1
rw-(0)
CAPD.0
0
rw-(0)
CAPD
05Bh
CAPD.4 CAPD.5 CAPD.6 CAPD.7
CAPD.x: 0: The input buffer for the pin enabled.
1: The input buffer for the pin is disabled.