Texas Instruments MSP430x1xx - Manual (Page 319)

Sampling
15-29
ADC12
15.7.5 Sample Timing Considerations
The A/D converter uses the charge redistribution method. Thus, when the
inputs are internally switched to sample the input analog signal, the switching
action causes displacement currents to flow into and out of the analog inputs.
These current spikes or transients occur at the leading and falling edges of the
sample pulse, and usually decay and settle before causing any problems
because typically the external time constant is less than that presented by the
internal effective RC. Internally, the analog inputs see an effective maximum
nominal RC of a 30 pF (C-array) capacitor in series with a 2-k
Ω
resistor (R
on
of switches). However, if the external dynamic-source impedance is large,
then these transients may not settle within the allocated sampling time to
ensure 12 bits of accuracy.
It is imperative that the proper sample timing be used for accurate conver-
sions. The next section discusses how to calculate the sample timing.
15.7.5.1 Simplified Sample-Timing Analysis
Using the equivalent circuit shown in Figure 15–25, the time required to charge
the analog-input capacitance from 0 to VS within 1/2 LSB can be derived as
follows.
Figure 15–25. Equivalent Circuit
R
s
r
i
V
S V
C
MSP430
C
i
V
I
V
I
= Input voltage at pin Ax
V
S
= External driving-source voltage
R
s
= Source resistance (must be real at input frequency)
r
i
= Input resistance (MUX-on resistance)
C
i
= Input capacitance
V
C
= Capacitance-charging voltage
The capacitance-charging voltage is given by:
V
C
+
V
S
ǒ
1–EXP
ǒ
–tc
Rt C
i
Ǔ
Ǔ
(1)
Where:
R
t
= R
s
+ Z
i
t
c
= Cycle time
The input impedance Z
i
is ~1 k
Ω
at 3.0 V, and is higher (~ 2 k
Ω
) at 1.8 V. The
final voltage to 1/2 LSB is given by:
V
C
(1
ń
2LSB)
+
V
S
–
ǒ
V
S
8192
Ǔ
(2)
Equating equation 1 to equation 2 and solving for cycle time tc gives:
V
S
–
ǒ
V
S
8192
Ǔ
+
V
S
ǒ
1–EXP
ǒ
–tc
Rt C
i
Ǔ
Ǔ
(3)