Texas Instruments TMS320C6712D User Manual
Texas Instruments Hardware
TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
1
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
D
Low-Price/High-Performance Floating-Point
Digital Signal Processor (DSP):
TMS320C6712D
− Eight 32-Bit Instructions/Cycle
− 150-MHz Clock Rate
− 6.7-ns Instruction Cycle Time
− 900 MFLOPS
D
Advanced Very Long Instruction Word
(VLIW) C67x
DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
D
Device Configuration
− Boot Mode: 8- and 16-Bit ROM Boot
− Little Endian, Big Endian
D
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D
16-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola
)
D
Two 32-Bit General-Purpose Timers
D
Flexible Software-Configurable PLL-Based
Clock Generator Module
D
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins
D
IEEE-1149.1 (JTAG
†
)
Boundary-Scan-Compatible
D
272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffix)
D
CMOS Technology
− 0.13-
µ
m/6-Level Copper Metal Process
D
3.3-V I/Os, 1.20
‡
-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2005, Texas Instruments Incorporated
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡ These values are compatible with existing 1.26V designs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Document Outline
- SPRS293A - TMS320C6712D
- features
- Table of Contents
- REVISION HISTORY
- GDP and ZDP BGA package (bottom view)
- description
- device characteristics
- device compatibility
- functional block and CPU (DSP core) diagram
- CPU (DSP core) description
- memory map summary
- peripheral register descriptions
- signal groups description
- DEVICE CONFIGURATIONS
- TERMINAL FUNCTIONS
- development support
- device support
- CPU CSR register description
- cache configuration (CCFG) register description
- interrupt sources and interrupt selector
- EDMA module and EDMA selector
- PLL and PLL controller
- general-purpose input/output (GPIO)
- power-down mode logic
- power-supply sequencing
- power-supply decoupling
- IEEE 1149.1 JTAG compatibility statement
- EMIF device speed
- EMIF big endian mode correctness
- bootmode
- reset
- absolute maximum ratings over operating case temperature range (unless otherwise noted)†
- recommended operating conditions
- electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)
- PARAMETER MEASUREMENT INFORMATION
- INPUT AND OUTPUT CLOCKS
- timing requirements for CLKIN†‡§ (see Figure 21)
- switching characteristics over recommended operating conditions for CLKOUT2ठ(see Figure 22)
- switching characteristics over recommended operating conditions for CLKOUT3†‡ ( see Figure 23)
- timing requirements for ECLKIN§ (see Figure 24)
- switching characteristics over recommended operating conditions for ECLKOUT†‡§ (see Figure 25)
- ASYNCHRONOUS MEMORY TIMING
- SYNCHRONOUS-BURST MEMORY TIMING
- SYNCHRONOUS DRAM TIMING
- HOLD\/HOLDA\ TIMING
- BUSREQ TIMING
- RESET TIMING
- EXTERNAL INTERRUPT TIMING
- MULTICHANNEL BUFFERED SERIAL PORT TIMING
- timing requirements for McBSP†‡ ( see Figure 41)
- switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 41)
- timing requirements for FSR when GSYNC = 1 (see Figure 42)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 43)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 43)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 44)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 44)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 45)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 45)
- timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 46)
- switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 46)
- TIMER TIMING
- GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
- JTAG TEST-PORT TIMING
- MECHANICAL DATA