Texas Instruments MSP430x1xx - Manual (Page 35)

Global Interrupt Structure
3-5
System Resets, Interrupts, and Operating Modes
3.2 Global Interrupt Structure
There are four types of interrupts:
- System reset
- Maskable
- Non-maskable
- (Non)-maskable
System reset (POR/PUC) is discussed in section 3.1.
Maskable interrupts are caused by:
- A watchdog-timer overflow (if timer mode is selected)
- Other modules with interrupt capability
Non-maskable interrupts are not maskable in any way. No individual interrupt
enable bit is implemented for them, and the general interrupt enable bit (GIE)
has no effect on them.
(Non)-maskable interrupts are not masked by the general interrupt enable bit
(GIE) but are individually enabled or disabled by an individual interrupt enable
bit. When a (non)-maskable interrupt is accepted, the corresponding interrupt
enable bit is automatically reset, therefore disabling the interrupt for execution
of the interrupt service routine (ISR). The RETI (return from interrupt)
instruction has no effect on the individual enable bits of the (non)-maskable
interrupts. So the software must set the corresponding interrupt enable bit in
the ISR before execution of the RETI instruction for the interrupt to be
re-enabled after the ISR.
A (non)-maskable NMI interrupt can be generated by an edge on the RST/NMI
pin (if NMI mode is selected), an oscillator fault occurs (if the oscillator fault
interrupt is enabled), or an access violation to the flash memory takes place
(if the access violation interrupt is enabled).