Texas Instruments MSP430x1xx - Manual (Page 179)

Introduction
11-3
Timer_B
each CCRx register to the corresponding compare latch (TBCLx) is user-
selectable to be either immediate, or on a timer event. See section 11.4.2.1 for
a complete discussion on using and configuring the compare latches.
The addition of the compare latch gives the user more control over when
exactly a compare period updates. In addition, multiple compare latches may
be grouped together allowing the compare period of multiple compare
registers to be updated simultaneously. This is useful for example when there
is a need to change the period or duty cycle of multiple PWM signals
simultaneously.
It is useful to note that in Timer_B’s default condition, the compare data is im-
mediately transferred from each CCRx register to the corresponding compare
latch. Therefore, in the default condition, the compare mode of Timer_B func-
tions identically to the compare mode of Timer_A.