Texas Instruments MSP430x1xx - Manual (Page 252)

Synchronous Operation
13-6
H) Second character is finished and sets the interrupt flag.
I) Master receives 2Ah and slave receives 74h (right justified).
Figure 13–4. Serial Synchronous Data Transfer
7 6 5 4 3 2 1 7 6 5 4 3 2 1
AB C D E F G HI
CKPL = 0
CKPLH= 0
CKPL = 1
CKPLH= 0
SIMO From
Master
SOMI From
Slave
STE
Master Interrupt
UTXIFG
Slave Interrupt
URXIFG
Shift Data Out
Shift Data In
Figure 13–5. Data Transfer Cycle
1 0 0 1 1 0 0 0
0 1 0 0 1 1 0 0
MSB LSB
1 0 1 1 0 0 0 0
0 1 0 1 1 0 0 0
MSB LSB
S
M
M
S
0 1 0 1 0 1 0 0
0 0 1 0 1 0 1 0
1 1 1 0 1 0 0 0
0 1 1 1 0 1 0 0
S
M
M
S
A: 98h> DSR
C,F: URXBUF
from Initial State
E: 54h> DSR
H,I: URXBUF
†
†
B: B0h> UTXBUF
C,D: DSR
G:E8h> UTXBUF
H,I: DSR
† In 7 bit mode, the MSB of RXBUF is always read as 0.
S: Slave M: Master