Texas Instruments MSP430x1xx - Manual (Page 205)

Timer_B Registers
11-29
Timer_B
11.6 Timer_B Registers
The Timer_B registers, described in Table 11–4, are word structured and must
be accessed using word instructions.
Table 11–4. Timer_B Registers
Register Short Form Register Type Address Initial State
Timer_B control TBCTL Read/write 180h POR reset
Timer_B register TBR Read/write 190h POR reset
Cap/com control 0 CCTL0 Read/write 182h POR reset
Capture/compare 0 CCR0 Read/write 192h POR reset
Cap/com control 1 CCTL1 Read/write 184h POR reset
Capture/compare 1 CCR1 Read/write 194h POR reset
Cap/com control 2 CCTL 2 Read/write 186h POR reset
Capture/compare 2 CCR2 Read/write 196h POR reset
Cap/com control 3 CCTL3 Read/write 188h POR reset
Capture/compare 3 CCR3 Read/write 198h POR reset
Cap/com control 4 CCTL4 Read/write 18Ah POR reset
Capture/compare 4 CCR4 Read/write 19Ah POR reset
Capture/compare 5 CCTL5 Read/write 18Ch POR reset
Capture/compare 5 CCR5 Read/write 19Ch POR reset
Capture/compare 6 CCTL6 Read/write 18Eh POR reset
Capture/compare 6 CCR6 Read/write 19Eh POR reset
Interrupt vector TBIV Read 11Eh (POR reset)
11.6.1 Timer_B Control Register TBCTL
The timer and timer operation control bits are located in the timer control
register (TBCTL) shown in Figure 11–27. All control bits are reset automati-
cally by the POR signal, but are not affected by the PUC signal. The control
register must be accessed using word instructions.
Figure 11–27.Timer_B Control Register TBCTL
rw-
(0)
15 0
Input Select Input Divider
Mode
Control
Un-
used
CLR TBIE TBIFG
TBCTL
180h
rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw-
(0) rw
(0) rw-
(0) rw-
(0) rw-
(0) w-
(0)
Group TBCL
Counter
Length
Un-
used
Bit 0: TBIFG: This flag indicates a timer overflow event.
Up mode:
TBIFG is set if the timer counts from TBCL0
value to 0000h.
Continuous mode: TBIFG is set if the timer counts from
TBR
(max)
to 0000h.
Up/down mode: TBIFG is set if the timer counts down from
0001h to 0000h.
Bit 1: Timer overflow interrupt enable (TBIE) bit. An interrupt request
from the timer overflow bit is enabled if this bit is set, and is disabled
if reset.