Texas Instruments MSP430x1xx - Manual (Page 214)

Timer_B Registers
11-38
11.6.4.3 Timer Interrupt Vector Register, Software Example, Timer_B7
The following software example describes the use of vector word TBIV of
Timer_B3 and the handling overhead. The numbers at the right margin show
the necessary cycles for every instruction. The example is written for
continuous mode: the time difference to the next interrupt is added to the
corresponding compare register.
; Software example for the interrupt part Cycles
;
; Interrupt handler for Capture/Compare Module 0.
; The interrupt flag CCIFG0 is reset automatically
;
TIMMOD0 ... ; Start of handler Interrupt latency 6
RETI 5
;
; Interrupt handler for Capture/Compare Modules 1 to 6.
; The interrupt flags CCIFGx and TBIFG are reset by
; hardware. Only the flag with the highest priority
; responsible for the interrupt vector word is reset.
TIM_HND
$ ; Interrupt latency 6
ADD &TBIV,PC ; Add offset to Jump table 3
RETI ; Vector 0: No interrupt 5
JMP TIMMOD1 ; Vector 2: Module 1 2
JMP TIMMOD2 ; Vector 4: Module 2 2
JMP TIMMOD3 ; Vector 6: Module 3 2
JMP TIMMOD4 ; Vector 8: Module 4 2
JMP TIMMOD5 ; Vector 10: Module 5 2
JMP TIMMOD6 ; Vector 12: Module 6 2
;
; Module 7. Timer Overflow Handler: the Timer Register is
; expanded into the RAM location TIMEXT (MSBs)
;
TIMOVH ; Vector 14: TIMOV Flag
INC TIMEXT ; Handle Timer Overflow 4
RETI 5
;
TIMMOD2 ; Vector 4: Module 2
ADD #NN,&CCR2 ; Add time difference 5
... ; Task starts here
RETI ; Back to main program 5
;
TIMMOD1 ; Vector 2: Module 1
ADD #MM,&CCR1 ; Add time difference 5
... ; Task starts here
RETI ; Back to main program 5
; The Module 3 handler shows a way to look if any other
; interrupt is pending: 5 cycles have to be spent, but
; 9 cycles may be saved if another interrupt is pending
;
TIMMOD3 ; Vector 6: Module 3
ADD #PP,&CCR3 ; Add time difference 5
... ; Task starts here
JMP TIM_HND ; Look for pending interrupts 2
;
.SECT ”VECTORS”,0FFF0h ; Interrupt Vectors
; The vector address may be different for different devices.
;
.WORD TIM_HND ; Vector for Capture/Compare
; Module 1..6 and timer overflow
; TBIFG
.WORD TIMMOD0 ; Vector for Capture/Compare
; Module 0