Avago Technologies LSI53C1000R User Manual
Avago Technologies Hardware
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Table of contents
Document Outline
- Chapter1 Introduction
- 1.1 General Description
- 1.2 Benefits of Ultra160 SCSI
- 1.3 Benefits of SURElink (Ultra160 SCSI Domain Validation) Technology
- 1.4 Benefits of LVDlink Technology
- 1.5 Benefits of TolerANT® Technology
- 1.6 Summary of LSI53C1000R Benefits
- Chapter2 Functional Description
- 2.1 PCI Functional Description
- 2.2 SCSI Functional Description
- 2.2.1 SCRIPTS Processor
- 2.2.2 Internal SCRIPTS RAM
- 2.2.3 64Bit Addressing in SCRIPTS
- 2.2.4 Hardware Control of SCSI Activity LED
- 2.2.5 Designing an Ultra160 SCSI System
- 2.2.6 Prefetching SCRIPTS Instructions
- 2.2.7 Opcode Fetch Burst Capability
- 2.2.8 Load and Store Instructions
- 2.2.9 JTAG Boundary Scan Testing
- 2.2.10 Parity/CRC/AIP Options
- 2.2.11 DMA FIFO
- 2.2.12 SCSI Data Paths
- 2.2.13 SCSI Bus Interface
- 2.2.14 Select/Reselect during Selection/Reselection
- 2.2.15 Synchronous Operation
- 2.2.16 Interrupt Handling
- 2.2.17 Interrupt Routing
- 2.2.18 Chained Block Moves
- 2.3 Parallel ROM Interface
- 2.4 Serial EEPROM Interface
- 2.5 Power Management
- Chapter3 Signal Descriptions
- 3.1 Signal Organization
- 3.2 Internal Pull-ups and Pull-downs
- 3.3 PCI Bus Interface Signals
- 3.4 SCSI Bus Interface Signals
- 3.5 General Purpose I/O (GPIO) Signals
- 3.6 Flash ROM and Memory Interface Signals
- 3.7 Test Interface Signals
- 3.8 Power and Ground Signals
- 3.9 MAD Bus Programming
- Chapter4 Registers
- 4.1 PCI Configuration Registers
- 4.2 SCSI Registers
- 4.3 SCSI Shadow Registers
- Chapter5 SCSI SCRIPTS Instruction Set
- 5.1 SCSI SCRIPTS
- 5.2 Block Move Instructions
- 5.3 I/O Instructions
- 5.4 Read/Write Instructions
- 5.5 Transfer Control Instructions
- 5.6 Memory Move Instructions
- 5.7 Load and Store Instructions
- Chapter6 Specifications
- 6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, S...
- Figure6.1 LVD Driver
- Table 6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/,...
- Figure6.2 LVD Receiver
- Table 6.5 DIFFSENS SCSI Signals
- Table 6.6 Input Capacitance
- Table 6.7 8 mA Bidirectional Signals – GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
- Table 6.8 4 mA Bidirectional Signals – MAD[7:0]
- Table 6.9 4 mA Output Signals – MAS[1:0]/, MCE/, MOE/_TESTOUT, MWE/, TDO
- Table 6.10 8 mA PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, ...
- Table 6.11 Input Signals – CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST/, TMS
- Table 6.12 8 mA Output Signals – INTA/, INTB/, ALT_INTA/, ALT_INTB/, REQ/, SERR/
- 6.2 TolerANT Technology Electrical Characteristics
- 6.3 AC Characteristics
- 6.4 PCI and External Memory Interface Timing Diagrams
- 6.4.1 Target Timing
- Table 6.17 PCI Configuration Register Read
- Figure6.11 PCI Configuration Register Read
- Table 6.18 PCI Configuration Register Write
- Figure6.12 PCI Configuration Register Write
- Table 6.19 Operating Register/SCRIPTS RAM Read, 32 Bits
- Figure6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits
- Table 6.20 Operating Register/SCRIPTS RAM Read, 64 Bits
- Figure6.14 Operating Register/SCRIPTS RAM Read, 64 Bits
- Table 6.21 Operating Register/SCRIPTS RAM Read, 32 Bits
- Figure6.15 Operating Register/SCRIPTS RAM Read, 32 Bits
- Table 6.22 Operating Register/SCRIPTS RAM Write, 64 Bits
- Figure6.16 Operating Register/SCRIPTS RAM Write, 64 Bits
- 6.4.2 Initiator Timing
- Table 6.23 Nonburst Opcode Fetch, 32-Bit Address and Data
- Figure6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
- Table 6.24 Burst Opcode Fetch, 32-Bit Address and Data
- Figure6.18 Burst Opcode Fetch, 32-Bit Address and Data
- Table 6.25 Back to Back Read, 32-Bit Address and Data
- Figure6.19 Back to Back Read, 32-Bit Address and Data
- Table 6.26 Back to Back Write, 32-Bit Address and Data
- Figure6.20 Back to Back Write, 32-Bit Address and Data
- Table 6.27 Burst Read, 32-Bit Address and Data
- Figure6.21 Burst Read, 32-Bit Address and Data
- Table 6.28 Burst Read, 64-Bit Address and Data
- Figure6.22 Burst Read, 64-Bit Address and Data
- Table 6.29 Burst Write, 32-Bit Address and Data
- Figure6.23 Burst Write, 32-Bit Address and Data
- Table 6.30 Burst Write, 64-Bit Address and Data
- Figure6.24 Burst Write, 64-Bit Address and Data
- 6.4.3 External Memory Timing
- Table 6.31 External Memory Read
- Figure6.25 External Memory Read
- Table 6.32 External Memory Write
- Figure6.26 External Memory Write
- Table 6.33 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
- Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
- Table 6.34 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
- Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
- Figure6.29 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle
- Figure6.30 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle
- Table 6.35 Slow Memory (³ 128 Kbytes) Read Cycle
- Figure6.31 Slow Memory (³ 128 Kbytes) Read Cycle
- Table 6.36 Slow Memory (³ 128 Kbytes) Write Cycle
- Figure6.32 Slow Memory (³ 128 Kbytes) Write Cycle
- Table 6.37 £ 64 Kbytes ROM Read Cycle
- Figure6.33 £ 64 Kbytes ROM Read Cycle
- Table 6.38 £ 64 Kbytes ROM Write Cycle
- Figure6.34 £ 64 Kbytes ROM Write Cycle
- 6.4.1 Target Timing
- 6.5 SCSI Timing Diagrams
- Table 6.39 Initiator Asynchronous Send
- Figure6.35 Initiator Asynchronous Send
- Table 6.40 Initiator Asynchronous Receive
- Figure6.36 Initiator Asynchronous Receive
- Table 6.41 Target Asynchronous Send
- Figure6.37 Target Asynchronous Send
- Table 6.42 Target Asynchronous Receive
- Figure6.38 Target Asynchronous Receive
- Table 6.43 SCSI-1 Transfers (SE 5.0 Mbytes)
- Table 6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.45 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
- Table 6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Qu...
- Figure6.39 Initiator and Target ST Synchronous Transfer
- Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
- Table 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Qu...
- Table 6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock
- Figure6.40 Initiator and Target DT Synchronous Transfer
- 6.6 Package Drawings
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback