Avago Technologies LSI53C1000R - Manual (Page 324)

6-42 Specifications
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.25 External Memory Read
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000R)
STOP/
(Driven by LSI53C1000R)
DEVSEL/
(Driven by LSI53C1000R)
AD[31:0]
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
1 2 3 4 5 6 7 8 9 10
LSI53C1000R-Data)
Addr
In
Byte Enable
LSI53C1000R-Data)
MAD
(Addr driven by LSI53C1000R;
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
t
1
t
2
t
1
t
2
CMD
In
t
1
t
2
t
1
t
2
t
1
t
3
t
13
t
11 t
12
t
15