Normal/fast memory – Avago Technologies LSI53C1000R User Manual
Page 333
PCI and External Memory Interface Timing Diagrams
6-51
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write Cycle
Figure 6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write Cycle
(Cont.)
CLK
(Driven by System)
1
2
3
4
5
6
7
8
9
10
MAD
(Driven by LSI53C1000R)
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
t
13
t
11
t
12
t
24
t
25
Write
Data
Valid
t
23
t
20
CLK
(Driven by System)
11
12
13
14
15
16
17
18
19
20
MAD
(Driven by LSI53C1000R)
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
21
t
24
t
25
t
21
Valid Write Data
t
20
t
23
t
22
t
26