Avago Technologies LSI53C1000R - Manual (Page 132)

4-20 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
DSCL Data_Scale [14:13]
The LSI53C1000R does not support the Data register.
Therefore, these two bits are always cleared.
DSLT Data_Select [12:9]
The LSI53C1000R does not support the Data register.
Therefore, these four bits are always cleared.
PEN PME_Enable 8
The LSI53C1000R always returns zero for this bit to
indicate that PME assertion is disabled.
R Reserved [7:2]
PWS[1:0] Power State [1:0]
Bits [1:0] determine the current power state of the
LSI53C1000R. They place the LSI53C1000R in a new
power state. Power states are defined as:
Refer to the Section 2.5, “Power Management,” for
descriptions of the Power Management States.
Register: 0x46
Bridge Support Extensions (PMCSR_BSE)
Read Only
BSE Bridge Support Extensions [7:0]
This register indicates PCI Bridge specific functionality.
The LSI53C1000R always returns 0x00.
0b00 D0
0b01 D1
0b10 D2
0b11 D3 hot
7 0
BSE
0 0 0 0 0 0 0 0