Avago Technologies LSI53C1000R - Manual (Page 158)

4-46 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x10–0x13
Data Structure Address (DSA)
Read/Write
DSA Data Structure Address [31:0]
This 32-bit register contains the base address used for all
Table Indirect calculations. The DSA register is usually
loaded prior to starting an I/O, but it is possible for a
SCRIPTS Memory Move to load the DSA during the I/O.
During any Memory-to-Memory Move operation, the
contents of this register are preserved. The power-up
value of this register is indeterminate.
Register: 0x14
Interrupt Status Zero (ISTAT0)
Read/Write
This is the only register that is accessible by the host CPU while an
LSI53C1000R is executing SCRIPTS (without interfering in the operation of
the function). It polls for interrupts if hardware interrupts are disabled. Read
this register after servicing an interrupt to check for stacked interrupts.
ABRT Abort Operation 7
Setting this bit aborts the current operation under
execution by the LSI53C1000R. If this bit is set and an
interrupt is received, clear this bit before reading the
DMA Status (DSTAT) register to prevent further aborted
interrupts from being generated. The sequence to abort
any operation is:
1. Set this bit.
2. Wait for an interrupt.
3. Read the Interrupt Status Zero (ISTAT0) register.
31 0
DSA
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
ABRT SRST SIGP SEM CON INTF SIP DIP
0 0 0 0 0 0 0 0