3 third dword, Figure5.14 memory move instructions – third dword, 7 load and store instructions – Avago Technologies LSI53C1000R User Manual
Page 279: Third dword, Load and store instructions, Memory move instructions – third dword, Section 5.7, “load and store instructions
Load and Store Instructions
5-37
Version 2.2
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5.6.3 Third Dword
This section describes the third Dword of the Memory Move Instruction
register.
Figure 5.14 Memory Move Instructions – Third Dword
TEMP Register
[31:0]
These bits contain the destination address for the
Memory Move.
If the destination address is in the 64-bit address space,
the bits are contained in the
Memory Move Write Selector (MMWS)
register.
5.7 Load and Store Instructions
The Load and Store instructions provide a more efficient way to move
data from/to memory to/from an internal register in the chip without using
the normal memory move instruction.
The load and store instructions are represented by two Dword opcodes.
The first Dword contains the
and
register values. The second Dword contains
the
DMA SCRIPTS Pointer Save (DSPS)
value. This is either the actual
memory location of where to load/store, or the offset from the
, depending on the value of bit 28
(DSA Relative).
For load operations where the data is read from the 64-bit address
space, the upper Dword of address resides in the
Memory Move Read Selector (MMRS)
register. For store operations
where the data is written to the 64-bit address space, the upper Dword
of address resides in the
Memory Move Write Selector (MMWS)
register.
31
0
TEMP Register
31
0
MMWS Register