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General purpose pin control (gpcntl), Register: 0x47 – Avago Technologies LSI53C1000R User Manual

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4-78

Registers

Version 2.2

Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.

Register: 0x47

General Purpose Pin Control (GPCNTL)
Read/Write

This register determines if the pins controlled by the

General Purpose (GPREG)

register are inputs or outputs. Bits [4:0] in

GPCNTL correspond to bits [4:0] in the GPREG register. When the bits
are enabled as inputs, an internal pull-up is also enabled.

To set the GPIO registers, follow these steps:

1.

Read the contents of the GPCNTL register.

2.

Read the contents of the GPREG register.

3.

Write the GPREG register.

4.

Write the GPCNTL register to control the pin for output/input.

ME

Master Enable

7

When the ME bit is set, the bus master state of the
device is presented on GPIO1. GPIO1 goes LOW when
the part is a bus master. When set, the ME bit is
independent of the setting of bit 1 (GPIO1). If the GPIO1
is configured as an input while the ME bit is set, the
Master bit still toggles the GPIO1 pin.

FE

Fetch Enable

6

If the FE bit is set, GPIO0 reflects when an internal
opcode fetch is being performed. GPIO0 goes LOW
when an opcode fetch is performed. When set, the FE bit
is independent of the setting of bit 0 (GPIO0). If GPIO0
is configured as an input, the Fetch bit still toggles
GPIO0.

LEDC

LED_CNTL

5

If the LED_CNTL bit is set GPIO0 reflects the state of the
SCSI bus, connected (GIO0 is LOW) or not connected
(GPIO0 is HIGH). This occurs if bit 6 (FE) is not set and
the chip is not currently performing an EEPROM
autodownload. This bit provides a hardware solution for
driving an external SCSI activity LED.

7

6

5

4

2

1

0

ME

FE

LEDC

GPIO[4:2]

GPIO[1:0]

0

0

x

0

1

1

1

1

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