Chip test four (ctest4), Register: 0x20, Register: 0x21 – Avago Technologies LSI53C1000R User Manual
Page 168
4-56
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x20
Reserved
This register is reserved.
Register: 0x21
Chip Test Four (CTEST4)
Read/Write
R
Reserved
7
FBL3
FIFO Byte Control 3
6
This bit is used with FBL[2:0]. Refer to Bits [2:0]
description in this register.
R
Reserved
[5:4]
MPEE
Master Parity Error Enable
3
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C1000R. A parity error during a
bus master write is detected by the target, and the
LSI53C1000R is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C1000R does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
FBL[2:0]
FIFO Byte Control
[2:0]
These bits steer the contents of the
register to the appropriate byte
lane of the 64-bit DMA FIFO. If the FBL3 bit is set, then
FBL2 through FBL0 determine which of eight byte lanes
can be read or written. When cleared, the byte lane read
or written is determined by the current contents of the
and
7
0
R
x
x
x
x
x
x
x
x
7
6
5
4
3
2
0
R
FBL3
R
MPEE
FBL[2:0]
0
0
0
0
0
0
0
0