Avago Technologies LSI53C1000R - Manual (Page 164)

4-52 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x18
Chip Test Zero (CTEST0)
Read/Write
FMT Byte Empty in DMA FIFO [7:0]
These bits identify the lower bytes in the DMA FIFO that
are empty. Each bit corresponds to a byte lane in the
DMA FIFO. For example, if byte lane three is empty, then
FMT bit 3 is set. The FMT flags indicate the status of
bytes at the bottom of the FIFO. Therefore, if all FMT bits
are set, the DMA FIFO is empty.
Register: 0x19
Chip Test One (CTEST1)
Read Only
FFL Byte Full in DMA FIFO [7:0]
These status bits identify the upper bytes in the
DMA FIFO that are full. Each bit corresponds to a byte
lane in the DMA FIFO. For example, if byte lane three is
full, then FFL bit 3 is set. The FFL flags indicate the
status of bytes at the top of the FIFO. Therefore, if all
FFL bits are set, the DMA FIFO is full.
7 0
FMT
1 1 1 1 1 1 1 1
7 0
FFL
0 0 0 0 0 0 0 0