Avago Technologies LSI53C1000R - Manual (Page 20)

1-2 Introduction
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
configuration and automatically tests and adjusts the SCSI transfer rate
to optimize interoperability. Three levels of Domain Validation are
provided, assuring robust system operation.
The LSI53C1000R has a local memory bus. This allows local storage of
the device’s BIOS ROM in flash memory or standard EPROMs. The
LSI53C1000R supports programming of local flash memory for BIOS
updates. The chip is packaged in a 456 Ball Grid Array (BGA).
Figure 1.1
shows a typical LSI53C1000R board application connected to external
ROM or flash memory.
Figure 1.1 Typical LSI53C1000R Board Application
LVDlink™ technology is the LSI Logic implementation of Low Voltage
Differential (LVD). LVDlink transceivers allow the LSI53C1000R to
perform either Single-Ended (SE) or LVD transfers. The LSI53C1000R
integrates a high-performance SCSI core, a 64-bit/66 MHz PCI bus
master DMA core, and the SCSI SCRIPTS™ processor to meet the
flexibility requirements of Ultra160 SCSI standards. It implements
multithreaded I/O algorithms with minimum processor intervention,
Flash ROM
Serial EEPROM
Memory Control
Block
LSI53C1000R
64-Bit/66MHz
PCI to
Single Channel
68-Pin
SCSI
Connector
SCSI Data,
Parity, and
Control Signals
PCI Interface
PCI Address, Data, Parity
Memory
Address/Data
Bus
GPIO/[1:0] Ultra160 SCSI
Controller
and
Terminator
and Control Signals