Avago Technologies LSI53C1000R - Manual (Page 209)

SCSI Registers 4-97
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Base Address Register Three (BAR3) (SCRIPTS RAM) .
In this mode, bits [12:0] of SCRATCH B always return
zeros. Writes to the SCRATCH B register have no effect.
Resetting the PCI Configuration Info Enable bit causes
the SCRATCH B register to return to normal operation.
Registers: 0x60–0x9F
Scratch Registers C–R (SCRATCHC–SCRATCHR)
Read/Write
These are general purpose user definable scratch pad registers. Apart
from CPU access, only register Read/Write, Memory Moves, and
Load/Stores directed at a SCRATCH register alter its contents. The
power-up values are indeterminate.
Registers: 0xA0–0xA3
Memory Move Read Selector (MMRS)
Read/Write
MMRS Memory Move Read Selector [31:0]
This register supplies AD[63:32] for data read operations
during Memory-to-Memory Moves and absolute address
LOAD operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
Chip Test Two (CTEST2) register. If this bit is set, the
Memory Move Read Selector (MMRS) register returns
bits [31:0] of the memory mapped operating register, PCI
Base Address Register Two (BAR2) (MEMORY) , when
read. In this mode, writes to the MMRS register affect no
change. Clearing the PCI Configuration Info Enable bit
causes the MMRS register to return to normal operation.
31 0
MMRS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0