Avago Technologies LSI53C1000R User Manual
Page 179
SCSI Registers
4-67
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
conditions are met), on writes to the
, on regular MMOV
instructions, and when an interrupt is generated. Based
on the burst length as determined by the values in the
register, the unit automatically
determines the maximum burst size that it is capable of
performing. If the burst threshold is set to 8 Dwords, the
prefetch unit fetches instructions in two bursts of
4 Dwords. If the burst threshold is set to 16 Dwords, or
greater, the prefetch unit fetches instructions in one burst
of 8 Dwords. Burst thresholds of less than 8 Dwords
cause the prefetch unit to be disabled. PCI Cache
commands (Read Line and Read Multiple) are issued if
PCI caching is enabled. Prefetching from SCRIPTS RAM
is not supported and is unnecessary due to the speed of
the fetches. When fetching from SCRIPTS RAM, the
setting of this bit has no effect on the fetch mechanism
from SCRIPTS RAM. The prefetch unit does not support
64-bit data instruction fetches across the PCI bus.
Prefetches of SCRIPTS instructions are 32 bits in width.
SSM
Single-Step Mode
4
Setting this bit causes the LSI53C1000R to stop after
executing each SCRIPTS instruction and to generate a
single step interrupt. When this bit is cleared, the
LSI53C1000R does not stop after each instruction. It
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit cleared. To restart the
LSI53C1000R after it generates a SCRIPTS Step
interrupt, read the
Interrupt Status Zero (ISTAT0)
and
registers to recognize and clear the
interrupt. Then set the START DMA bit in this register.
IRQM
IRQ Mode
3
When set, this bit enables a totem pole driver for the
INTA/ pin. When cleared, this bit enables an open drain
driver for the INTA/ pin with an internal weak pull-up. The
bit should remain cleared to retain full PCI compliance.