Avago Technologies LSI53C1000R User Manual
Page 60
2-30
Functional Description
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
•
The
register:
–
Bit 7, CRCERR (CRC Error), indicates whether or not a CRC
error has been detected during a DT Data In SCSI transfer. This
bit is independent of the DCRCC bit setting. To clear this
condition, either write this bit to a one or read the SIST0 and
SIST1 registers. When CRC checking and the Parity/CRC/AIP
Error interrupt are both enabled, CRCERR is mirrored in the
SIST0 register, bit 0, as a Parity/CRC/AIP error.
–
Bit 6 is reserved.
–
Bit 5, ENAS (Enable CRC Auto Seed), is set to cause the CRC
logic to reseed itself automatically after every CRC check
performed during DT Data In SCSI transfers. When this bit is
cleared, the SCSI control logic controls when the CRC logic is
reseeded.
–
Bit 4, TSTSD (Test CRC Seed), is set to cause the CRC logic to
reseed itself immediately. Do not set this bit during normal
operation as it may cause corrupt CRCs to be generated.
–
Bit 3, TSTCHK (Test CRC Check), is set to cause the CRC logic
to initiate a CRC check. Do not set this bit during normal
operation because it creates spurious CRC errors.
–
Bit 2, TSTADD (Test CRC Accumulate), is set to cause the CRC
block to include the value present in the input register in the current
CRC calculation. A new output CRC value results. Do not set this
bit during normal operation because corrupt CRC values result.
–
Bits [1:0], CRCDSEL[1:0] (CRC Data Register Selector), control
the data visible in the CRC Data register.
•
The
register:
–
Bits [31:0] CRCDATA (CRC Data). The value in this register is
dependent upon the setting of the CRCDSEL bits.