Avago Technologies LSI53C1000R User Manual
Page 182
4-70
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
SEL
Selected
5
When set, this bit indicates the LSI53C1000R is selected
by a SCSI initiator device. For this to occur, set the Enable
Response to Selection bit in the
register.
RSL
Reselected
4
When set, this bit indicates the LSI53C1000R is
reselected by a SCSI target device. For this to occur, set
the Enable Response to Reselection bit in the
register.
SGE
SCSI Gross Error
3
The following conditions are considered SCSI Gross Errors:
•
Offset Underflow occurs in target mode when a
SACK/ signal is received before the corresponding
SREQ/ signal has been sent.
•
Offset Overflow occurs in initiator mode when an
SREQ/ signal is received and causes the maximum
offset, as defined by the MO[5:0] bits in the SXFER
register, to be exceeded.
•
In initiator mode, a phase change occurs with an
outstanding SREQ/SACK offset.
•
Residual Data in SCSI FIFO occurs when a transfer
other than Synchronous Data Received is started with
data left in the SCSI Synchronous Receive FIFO.
•
Multiple CRC Requests occur when, during a
synchronous DT transfer, multiple CRC requests are
received within the same offset.
•
A request for a Pad CRC word is received without the
subsequent CRC word requests.
•
A phase change occurs without a CRC Request.
Note:
Checking for this condition can be disabled by setting the
DISCRC bit in the CRCCNTL0 register.
•
An illegal Force CRC Request Block Move is executed.
•
A SCRIPTS RAM parity error.
Note:
The
register indicates which
condition caused an SGE SCSI interrupt. This register is
shadowed behind the