Avago Technologies LSI53C1000R - Manual (Page 329)

PCI and External Memory Interface Timing Diagrams 6-47
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.26 External Memory Write (Cont.)
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000R)
STOP/
(Driven by LSI53C1000R)
DEVSEL/
(Driven by LSI53C1000R)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
11 12 13 14 15 16 17 18 19 20
MAD
(Driven by LSI53C1000R)
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
21
t
24
t
22
t
25
t
26
t
21
t
20
t
23
(Driven by Master)
(Driven by Master)
Data Out