Avago Technologies LSI53C1000R - Manual (Page 88)

2-58 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
instruction is executed, the data transfer occurs similar to that of the
regular Block Move instruction. It is recommended that all Block Move
instructions be Chained Block Moves.
For send data (Data-Out for the initiator or Data-In for the target), a Chained
Block Move instruction indicates that if a partial transfer terminates, the
Chained Block Move the WSS flag is set. The low-order byte should be
stored in the lower byte of the
SCSI Output Data Latch (SODL) register for
asynchronous transfers or in the chain byte holding register for
synchronous transfers and not sent across the SCSI bus. Without the
Chained Block Move instruction, the last low-order byte would be sent
across the SCSI bus. The starting byte count represents data bytes
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an initiator Chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes are
transferred out of memory to the SCSI controller. Four bytes are transferred
from the SCSI controller across the SCSI bus and one byte is temporarily
stored as described above, waiting to be “married” with the first byte of the
next Block Move instruction. If the WSS bit is set at the start of a data send
command, the first byte of the transfer is assumed to be the high-order byte
and is “married” with the stored byte (low-order byte) before the two bytes
are sent across the SCSI bus. It is recommended that all Block Move
instructions be Chained Block Moves.
2.3 Parallel ROM Interface
The LSI53C1000R supports up to 1 Mbyte of external memory in binary
increments from 16 Kbytes to allow the use of expansion ROM for add-in
PCI cards. This interface is designed for low-speed operations such as
downloading instruction code from ROM; it is not intended for dynamic
activities such as executing instructions.
System requirements include the LSI53C1000R, two or three external
8-bit address holding registers (HCT273 or HCT374), and the appropriate
memory device. The 4.7 k
Ω
pull-up resistors on the MAD bus require HC
or HCT external components to be used. Pull-up resistors on the 8-bit
bidirectional memory bus at power-up determine the memory size and
speed. The LSI53C1000R senses this bus shortly after the release of the
Reset signal and configures the Expansion ROM Base Address register
and the memory cycle state machines for the appropriate conditions.