Avago Technologies LSI53C1000R - Manual (Page 250)

5-8 SCSI SCRIPTS Instruction Set
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
64-Bit Addressing
If the Enable 64-bit Table Indirect Block Move
(EN64TIBMV) bit is cleared, table indirect block moves
remain as 2 Dword opcodes plus a 2 Dword table entry.
The upper 32 bits of the address are copied from the
Static Block Move Selector (SBMS) when performing
data transfers during block move operations. The SBMS
register must be loaded manually.
If the Enable 64-bit Table Indirect Block Move
(EN64TIBMV) bit is set and the 64-bit Table Indirect Index
Mode (64TIMOD) bit is cleared, bits [28:24] of the first
Dword of the table entry (where the byte count is located)
select one of the 16 scratch registers or any of the six 64-bit
selector registers as a selector for the upper 32-bit address.
Refer to the Table Indirect Index mode mapping table for a
breakdown of index values and the corresponding registers
selected. The selected address is automatically loaded into
the
DMA Next Address 64 (DNAD64) register.
Note: If EN64TIBMV is set and 64TIMOD is set, bits [31:24] of the
first Dword of the table entry (where the byte count is located)
are loaded directly into
DMA Next Address 64 (DNAD64) to
provide a 40-bit address.
The format for the table indirect entries for each mode is
shown as follows. The table for Table Indirect block
moves upper 32-bit address locations summarizes the
available modes for table indirect block moves.
Index Mode 0 (64TIMOD clear) table entry format:
Index Mode 1 (64TIMOD set) table entry format:
Table Indirect block moves upper 32-bit address locations:
31 29 28 24 23 0
R Sel Index Byte Count
Source/Destination Address [31:0]
31 24 23 0
Src/Dest Addr [39:32] Byte Count
Source/Destination Address [31:0]