Avago Technologies LSI53C1000R - Manual (Page 160)

4-48 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
to notify an external processor of a predefined condition
while SCRIPTS are running. The external processor may
also notify the LSI53C1000R of a predefined condition,
and the SCRIPTS processor may take action while
SCRIPTS are executing.
CON Connected 3
This bit is automatically set any time the LSI53C1000R is
connected to the SCSI bus as an initiator or as a target.
It is set after successfully completing selection or when
the LSI53C1000R responds to a bus-initiated selection or
reselection. It is also set after the SCSI function wins
arbitration when operating in the low level mode. When
this bit is cleared, the LSI53C1000R is not connected to
the SCSI bus.
INTF Interrupt-on-the-Fly 2
This bit is asserted by an INTFLY instruction during
SCRIPTS execution. SCRIPTS programs do not halt when
the interrupt occurs. This bit can notify a service routine,
running on the main processor while the SCRIPTS
processor is still executing a SCRIPTS program. If this bit
is set, when the
Interrupt Status Zero (ISTAT0) register is
read it is not automatically cleared. To clear this bit, write
a one to it. The reset operation is self-clearing.
Note: If the INTF bit is set but SIP or DIP is not set, do not
attempt to read the other chip status registers. An
interrupt-on-the-fly must be cleared before servicing any
other interrupts indicated by SIP or DIP.
After it has been set, this bit must be written to one to clear it.
SIP SCSI Interrupt Pending 1
This status bit is set when an interrupt condition is
detected in the SCSI portion of the LSI53C1000R. The
following conditions cause a SCSI interrupt to occur:
•
A phase mismatch (initiator mode) or SATN/ becomes
active (target mode)
•
An arbitration sequence completes
•
A selection or reselection time-out occurs
•
The LSI53C1000R is selected
•
The LSI53C1000R is reselected