Avago Technologies LSI53C1000R - Manual (Page 26)

1-8 Introduction
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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Supports variable block size and scatter/gather data transfers.
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Performs sustained Memory-to-Memory DMA transfers to
approximately 100 Mbytes/s.
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Minimizes the SCSI I/O start latency.
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Performs complex bus sequences without interrupts, including
restoring data pointers.
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Reduces Interrupt Service Routine (ISR) overhead through a unique
interrupt status reporting method.
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Includes SCSI Interrupt Steering Logic (SISL) for RAID Ready SCSI
on mainboard applications with a separate interrupt for routing to a
RAID adapter.
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Supports Load/Store SCRIPTS instructions to increase the
performance of data transfers to and from the chip registers without
using PCI cycles.
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Includes SCRIPTS support of 64-bit addressing.
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Supports target disconnect and later reconnect with no interrupt to
the system processor.
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Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
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Supports expanded Register Move instructions to support additional
arithmetic capability.
1.6.2 PCI Performance
The LSI53C1000R:
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Complies with PCI 2.2 specification.
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Supports a 64-bit/66 MHz PCI interface for 528 Mbytes/s bandwidth
that:
– Can function in a 32-bit or 64-bit PCI slot
– Operates at 33 or 66 MHz
– Supports dual address cycle (DAC) generation for all SCRIPTS
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Bursts 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers
across the PCI bus.
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Supports 32-bit or 64-bit word data bursts with variable burst lengths.