Avago Technologies LSI53C1000R - Manual (Page 16)

xvi
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
6.5 DIFFSENS SCSI Signals 6-4
6.6 Input Capacitance 6-4
6.7 8 mA Bidirectional Signals – GPIO0_FETCH/,
GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
6-5
6.8 4 mA Bidirectional Signals – MAD[7:0] 6-5
6.9 4 mA Output Signals – MAS[1:0]/, MCE/,
MOE/_TESTOUT, MWE/, TDO
6-5
6.10 8 mA PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/,
FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR,
PAR64, REQ64/, ACK64/
6-6
6.11 Input Signals – CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI,
TEST_HSC, TEST_RST/, TMS
6-6
6.12 8 mA Output Signals – INTA/, INTB/, ALT_INTA/,
ALT_INTB/, REQ/, SERR/
6-6
6.13 TolerANT Technology Electrical Characteristics
for SE SCSI Signals
6-7
6.14 External Clock 6-11
6.15 Reset Input 6-12
6.16 Interrupt Output 6-13
6.17 PCI Configuration Register Read 6-16
6.18 PCI Configuration Register Write 6-17
6.19 Operating Register/SCRIPTS RAM Read, 32 Bits 6-18
6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 6-19
6.21 Operating Register/SCRIPTS RAM Read, 32 Bits 6-21
6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 6-22
6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-24
6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-26
6.25 Back to Back Read, 32-Bit Address and Data 6-28
6.26 Back to Back Write, 32-Bit Address and Data 6-30
6.27 Burst Read, 32-Bit Address and Data 6-32
6.28 Burst Read, 64-Bit Address and Data 6-34
6.29 Burst Write, 32-Bit Address and Data 6-36
6.30 Burst Write, 64-Bit Address and Data 6-38
6.31 External Memory Read 6-41
6.32 External Memory Write 6-45
6.33 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-48