Scsi test four (stest4), Scsi input data latch (sidl), Register: 0x52 – Avago Technologies LSI53C1000R User Manual
Page 201
SCSI Registers
4-89
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0x50–0x51
SCSI Input Data Latch (SIDL)
Read Only
SIDL
SCSI Input Data Latch
[15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery.
Asynchronous Data received from the SCSI bus can be
read from this register. When receiving asynchronous
SCSI data, the data flows into this register and out to the
host FIFO. This register differs from the
register; the
contains latched data and
the
always contains exactly
what is currently on the SCSI data bus. Reading this
register causes the SCSI parity bit to be checked, and
causes a parity error interrupt if the data is invalid. The
power-up values are indeterminate.
Register: 0x52
SCSI Test Four (STEST4)
Read Only
SMODE[1:0]
SCSI Mode
[7:6]
These bits contain the encoded value of the SCSI
operating mode that is indicated by the voltage level
sensed at the DIFFSENS pin. The incoming SCSI signal
goes to a pair of analog comparators that determine the
voltage window of the DIFFSENS signal. These voltage
windows indicate LVD, SE, or HVD operation. The bit
values are defined in the following table. When the HVD
mode is detected, all of the LSI53C1000R 3-state outputs
go to the high impedance state.
15
0
SIDL
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7
6
5
0
SMODE[1:0]
R
x
x
0
0
0
0
0
0