Avago Technologies LSI53C1000R - Manual (Page 384)

IX-12 Index
block move 5-4
I/O 5-14
read/write 5-23
interface signals 3-10
interrupt 2-51
enable one (SIEN1) 2-48 , 4-71
enable zero (SIEN0) 2-35 , 2-48 , 4-69
status one (SIST1) 2-47 , 2-48 , 2-50 , 2-52 , 4-76 ,
4-126
status zero (SIST0) 2-35 , 2-47 , 2-48 , 2-50 , 2-52 ,
4-73
interrupt pending (SIP) 4-48
low level mode (LOW) 4-87
LVD 2-39
mode (SMODE[1:0]) 4-89
MSG/ signal (MSG) 4-43
new phases on the SCSI bus 2-23
output control latch (SOCL) 4-37
output data latch (SODL) 4-90
parity errors and interrupts 2-36
parity/CRC error (PAR) 4-71
performance 1-7
phase 5-12 , 5-29
phase mismatch - initiator mode 4-69
receive rate 2-43
registers 4-21
reset condition (RST) 4-71
RST/ received (RST) 4-75
RST/signal (RST) 4-43
SCRIPTS operation 5-1
sample instruction 5-2
SDP0/ parity signal (SDP0) 4-43
SDP1/ parity signal (SDP1) 4-45
selected as ID (SSAID[3:0]) 4-83
selector ID (SSID) 4-38
send rate 2-43
single-ended 2-39
SODL register 2-57
status one (SSTAT1) 2-35 , 4-43
status two (SSTAT2) 2-35 , 4-44
status zero (SSTAT0) 2-35 , 4-42
synchronous offset maximum (SOM) 4-84
synchronous offset zero (SOZ) 4-84
synchronous operation 2-41
synchronous receive 2-39
synchronous send 2-38
termination 2-39
test four (STEST4) 4-89
test one (STEST1) 4-85
test three (STEST3) 4-87
test two (STEST2) 4-86
test zero (STEST0) 4-83
timer one (STIME1) 4-81
timer zero (STIME0) 4-79
timing diagrams 6-62
TolerANT technology 1-6
transfer (SXFER) 4-33
Ultra160 SCSI 2-22
valid (VAL) 4-38
wide residue (SWIDE) 4-77
wide SCSI receive bit 2-56
wide SCSI send bit 2-56
SCSI-1
transfers (single-ended 5.0 Mbytes) 6-64
SCSI-2
fast transfers 6-65 , 6-67
SD[15:0]+- 3-10
second dword 5-13 , 5-22 , 5-24 , 5-33 , 5-36 , 5-40
select 2-18
during selection 2-41
instruction 5-17
with ATN/ 5-20
with SATN/ on a start sequence (WATN) 4-25
selected (SEL) 4-70 , 4-74
selection or reselection time-out (STO) 4-72 , 4-76
selection response logic test (SLT) 4-84
semaphore (SEM) 4-47
send rate calculation 2-43
serial EEPROM
data format 2-61
interface 2-60
SERR/ 3-9
SERR/enable (SE) 4-3
set instruction 5-16
SCRIPTS 5-18
set/clear
carry 5-21
SACK/ 5-21
SATN/ 5-22
target mode 5-21
SIDL
least significant byte full (ILF) 4-42
most significant byte full (ILF1) 4-44
SIEN0 2-48
SIEN1 2-48
signal process (SIGP) 4-47 , 4-53
signaled system error (SSE) 4-5
simple arbitration 4-23
single
address cycles 2-21
ended SCSI signals 6-7
step interrupt (SSI) 4-40 , 4-65
step mode (SSM) 4-67
transition
data-in 2-23
data-out 2-23