Scratch register b (scratchb), Registers: 0x5c–0x5f – Avago Technologies LSI53C1000R User Manual
Page 208
4-96
Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
DSKEW[1:0]
Setup Data Skew Control
[3:2]
These bits control the amount of skew between the SCSI
REQ/ACK signal and the SCSI data signals during setup.
The skew is affected only if the ENDSKEW bit is set.
Note:
These bits are used for Ultra160 SCSI Domain Validation only
and should not be set during normal data transfer operations.
LVDDL[1:0]
LVD Drive Strength Select
[1:0]
These bits control the drive level of the LVD pad drivers.
Note:
This feature is for Ultra160 SCSI Domain Validation testing
environments only and should not be set during normal
data transfer operations.
The following table shows the relative strength increase
or decrease based on the LVDDL values.
Registers: 0x5C–0x5F
Scratch Register B (SCRATCHB)
Read/Write
SCRATCHB
Scratch Register B
[31:0]
This is a general purpose user definable scratchpad
register. Apart from CPU access, only register
Read/Write and Memory Moves directed at the
SCRATCH register alter its contents. The power-up
values are indeterminate. A special mode of this register
can be enabled by setting the PCI Configuration Info
Enable bit in the
register. If this
bit is set, bits [31:13] of the
register return bits
[31:13] of the PCI
LVDDL
Drive Level
00
Nominal
01
−
20% Nominal
10
+20% Nominal
11
Reserved
31
0
SCRATCHB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0