Avago Technologies LSI53C1000R - Manual (Page 162)

4-50 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
R Reserved [7:3]
FLSH Flushing 2
If this bit is set, the chip is flushing data from the
DMA FIFO. If cleared, no flushing is occurring. This bit is
read only. Writes do not affect the value of this bit.
SRUN SCRIPTS Running 1
If this bit is set, the SCRIPTS engine is currently fetching
and executing SCRIPTS instructions. If it is cleared, the
SCRIPTS engine is not active. This bit is read only.
Writes do not affect the value of this bit.
SI SYNC_IRQD 0
Setting this bit disables the INTA/ pin for the
LSI53C1000R, except for the SCSI gross error, bus fault,
residual data in SCSI FIFO, and data underflow
interrupts. Clearing this bit enables normal operation of
the INTA/ pin. If the INTA/ is already asserted and this bit
is set, INTA/ remains asserted until the interrupt is
serviced. At this point the interrupt line is blocked for
future interrupts until this bit is cleared. In addition, this bit
may be read and written while SCRIPTS are executing.
7 3 2 1 0
R FLSH SRUN SI
0 0 0 0 0 0 0 0