Avago Technologies LSI53C1000R - Manual (Page 101)

PCI Bus Interface Signals 3-7
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
3.3.3 Interface Control Signals
Table 3.4 describes the Interface Control Signals group.
PAR64 AA24 T/S 8 mA PCI Parity64 is the even parity bit that protects
the AD[63:32] and C_BE[7:4]/ lines. During
the address phase, the address and
command bits are covered. During the data
phase, both data and byte enables are
covered.
Table 3.3 Address and Data Signals (Cont.)
Name Bump Type Strength Description
Table 3.4 Interface Control Signals
Name Bump Type Strength Description
ACK64/ AB20 S/T/S 8 mA PCI Acknowledge 64-bit transfer is driven by the current bus
target to indicate its ability to transfer 64-bit data.
REQ64/ AD22 S/T/S 8 mA PCI Request 64-bit transfer is driven by the current bus master
to indicate a request to transfer 64-bit data.
FRAME/ AB15 S/T/S 8 mA PCI Cycle Frame is driven by the current master to indicate the
beginning and duration of an access. FRAME/ is asserted
to indicate that a bus transaction is beginning. While
FRAME/ is deasserted, either the transaction is in the final
data phase or the bus is idle.
TRDY/ AE16 S/T/S 8 mA PCI Target Ready indicates the target’s ability to complete the
current data phase of the transaction. TRDY/ is used with
IRDY/. A data phase is completed on any clock when both
TRDY/ and IRDY/ are sampled asserted. During a read,
TRDY/ indicates that valid data is present on the AD bus.
During a write, it indicates that the target is prepared to
accept data.
IRDY/ AE15 S/T/S 8 mA PCI Initiator Ready indicates the initiator’s ability to complete
the current data phase of the transaction. IRDY/ is used with
TRDY/. A data phase is completed on any clock when both
IRDY/ and TRDY/ are sampled asserted. During a write,
IRDY/ indicates that valid data is present on the AD bus.
During a read, it indicates that the master is prepared to
accept data.