Avago Technologies LSI53C1000R - Manual (Page 219)

SCSI Registers 4-107
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Table 4.4 DT Transfer Rates
Clock
(MHz)
Divisor
Number
Xclks
1
Base
Period
(ns)
Receive Rate
(Megatransfers/)
Send Rate
(Megatransfers/)
160 1 0 6.25 80.00 80.00
160 1 1 6.25 80.00 64.00
160 1 2 6.25 80.00 53.33
160 1 3 6.25 80.00 45.71
160 1 4 6.25 80.00 40.00
160 1.5 0 9.38 53.33 53.33
160 1.5 1 9.38 53.33 42.67
160 1.5 2 9.38 53.33 35.56
160 1.5 3 9.38 53.33 30.48
160 1.5 4 9.38 53.33 26.67
160 2 0 12.50 40.00 40.00
160 2 1 12.50 40.00 32.00
160 2 2 12.50 40.00 26.67
160 2 3 12.50 40.00 22.86
160 2 4 12.50 40.00 20.00
160 3 0 18.75 26.67 26.67
160 3 1 18.75 26.67 21.33
160 3 2 18.75 26.67 17.78
160 3 3 18.75 26.67 15.24
160 3 4 18.75 26.67 13.33