Avago Technologies LSI53C1000R - Manual (Page 51)

SCSI Functional Description 2-21
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.3 64-Bit Addressing in SCRIPTS
The PCI interface for the LSI53C1000R provides 64-bit address and data
capability in the initiator mode. The chip can also respond to 64-bit
addressing in the target mode.
DACs can be generated for all SCRIPTS operations. There are six
selector registers that hold the upper Dword of a 64-bit address. All but
one of these is static and requires manual loading using a CPU access,
a Load and Store instruction, or a memory move instruction. One of the
selector registers is dynamic and is used during 64-bit direct block moves
only. All selectors default to zero, meaning the LSI53C1000R powers-up
in a state where only Single Address Cycles (SACs) are generated.
When any of the selector registers are written to a nonzero value, DACs
are generated.
Direct, Table Indirect and Indirect Block Moves, Memory-to-Memory Moves,
Load/Stores, and Jumps are all instructions with 64-bit address capability.
Note: Crossing the 4 Gbyte boundary on any one SCRIPTS
operation is not permitted. Therefore, software must handle
all such transactions.
2.2.4 Hardware Control of SCSI Activity LED
The LSI53C1000R controls an LED through the GPIO_0 pin to indicate
that it is connected to the SCSI bus. This function was previously
handled by a software driver.
Bit 3 (CON), in the Interrupt Status Zero (ISTAT0) register, is presented
at the GPIO_0 pin when the following occurs:
•
Bit 5 (LED_CNTL) in the General Purpose Pin Control (GPCNTL)
register is set,
•
Bit 6 (Fetch Enable) in the General Purpose Pin Control (GPCNTL)
register is cleared,
•
The LSI53C1000R is not performing an EEPROM autodownload.
The CON (Connected) bit in Interrupt Status Zero (ISTAT0) is set anytime
the LSI53C1000R is connected to the SCSI bus either as an initiator or
a target. This happens after the LSI53C1000R has successfully