Avago Technologies LSI53C1000R - Manual (Page 27)

Summary of LSI53C1000R Benefits 1-9
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
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Prefetches up to 8 Dwords of SCRIPTS instructions.
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Bursts SCRIPTS opcode fetches across the PCI bus.
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Performs zero wait-state bus master data bursts up to 528 Mbytes/s
(@ 66 MHz).
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Supports PCI Cache Line Size (CLS) register.
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Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
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Complies with PCI Bus Power Management Specification Rev 1.1.
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Complies with PC99.
1.6.3 Integration
The following features ease integration of the LSI53C1000R into a
system.
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Ultra160 SCSI PCI Controller.
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Integrated LVD transceivers.
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Full 32-bit or 64-bit PCI DMA bus master.
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Memory-to-Memory Move instructions allow use as a third-party PCI
bus DMA controller.
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Integrated SCRIPTS processor.
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Pin to pin compatible with the LSI53C1020 and subsequent chips.
1.6.4 Ease of Use
The following features of the LSI53C1000R make the device user friendly.
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The LSI53C1000R is pin compatible with the LSI53C1020.
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Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS
storage.
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Reduced SCSI development effort.
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Compiler-compatible with existing LSI53C7XX and LSI53C8XX
family SCRIPTS.
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Direct connection to PCI and SCSI SE and LVD.
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Development tools and sample SCSI SCRIPTS available.