Avago Technologies LSI53C1000R - Manual (Page 50)

2-20 Functional Description
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
2.2.2 Internal SCRIPTS RAM
The LSI53C1000R has 8 Kbytes (2048 x 32 bits) of internal, general
purpose RAM. The RAM is designed for SCRIPTS program storage, but
is not limited to this type of information. When the chip fetches SCRIPTS
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. In
addition, any SCRIPTS instruction that contains a source or destination
address residing in SCRIPTS RAM memory space remains internal to
the chip and does not generate PCI cycles. SCRIPTS instructions able
to access SCRIPTS RAM memory space in this manner include
Memory-to-Memory Moves, Load/Stores, and Block Moves. While an
internal cycle is occurring, any external PCI slave cycle is retried on the
PCI bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit
in the
Chip Control Zero (CCNTL0) register disables this feature.
SCRIPTS RAM should be initialized before it is read. Reading
SCRIPTS RAM before initialization sets the SCRIPTS RAM parity bit,
bit 7, in the
Shadowed SCSI SGE Status 0 register.
PCI system BIOS can relocate the RAM anywhere in the 64-bit address
space.
Base Address Register Three (BAR3) (SCRIPTS RAM) and
Base Address Register Four (BAR4) (SCRIPTS RAM) , in the PCI
configuration space, contain the base address of the internal RAM. To
simplify SCRIPTS instruction loading, the base address of the RAM
appears in the
Scratch Register B (SCRATCHB) register when bit 3 of the
Chip Test Two (CTEST2) register is set. The upper 32 bits of a 64-bit base
address are in the SCRIPT Fetch Selector (SFS) register. The RAM is
byte-accessible from the PCI bus and is visible to any bus mastering device
on the bus. External, CPU accesses to the RAM follow the same timing
sequence as a standard slave register access, except that the required
target wait states drop from 5 to 3. SCRIPTS RAM must first be written
before being read in order to initialize SCRIPTS RAM parity. If a SCRIPTS
RAM parity error is encountered, a SCSI Gross Error interrupt is signaled.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C1000R, refer to
Chapter 5, “SCSI SCRIPTS Instruction Set.”