Avago Technologies LSI53C1000R - Manual (Page 377)

Index IX-5
burst
length (BL[1:0]) 4-62
length bit 2 (BL2) 4-58
opcode fetch enable (BOF) 4-64
size selection 2-7
burst opcode fetch 32-bit address and data 6-26
bus
command and byte enables 3-6
fault (BF) 4-40 , 4-65
byte
count 5-40
empty in DMA FIFO (FMT[7:0]) 4-52
full in DMA FIFO (FFL[7:0]) 4-52
C
C_BE[3:0]/ 2-3
C_BE[7:0]/ 3-6
cache line size
(CLS[7:0]) 2-8 , 4-7
enable (CLSE) 2-8 , 4-66
register 2-7 , 2-11
cache mode, See PCI cache mode 2-11
call instruction 5-28
cap_ID (CID[7:0]) 4-18
capabilities pointer (CP[7:0]) 4-15
capability ID register 4-18
carry test 5-31
chained block moves 2-55 , 2-57
chained mode (CHM) 4-30
change bus phases 2-18
chip
control one (CCNTL1) 4-93
control zero (CCNTL0) 4-91
test five (CTEST5) 2-8 , 4-57
test four (CTEST4) 2-35 , 4-56
test one (CTEST1) 4-52
test six (CTEST6) 4-58
test three (CTEST3) 2-9 , 2-12 , 4-54
test two (CTEST2) 4-53
test zero (CTEST0) 4-52
CHMOV 2-55
class code register 4-7
clear DMA FIFO (CLF) 2-51 , 4-55
clear instruction 5-16
clear SCSI FIFO (CSF) 2-51 , 4-88
CLK 3-5
clock 3-5
quadrupler 2-31
command register 2-12
compare
data 5-32
phase 5-32
configuration
read command 2-6
space 2-3
write command 2-7
configured
as I/O (CIO) 4-53
as memory (CM) 4-53
connected (CON) 4-28 , 4-48
CRC 1-4 , 2-23
control and generation 2-34
disable checking 4-121
disable protocol checking 4-121
options 2-34
CRC-32 1-4
cumulative SCSI byte count (CSBC) 4-120
current
function of input voltage 6-9
function of output voltage 6-10
cycle frame 3-7
cyclic redundancy check 1-4
D
D0 2-62
D1 2-62
D1_Support (D1S) 4-19
D2 2-63
D2_Support (D2S) 4-19
D3 2-63
D3cold 2-63
D3hot 2-63
DACs 2-21
data
(DATA[7:0]) 4-21
compare mask 5-32
compare value 5-33
parity error reported (DPR) 4-6
paths 2-37
structure address (DSA) 4-46
data_scale (DSCL) 4-20
data_select (DSLT) 4-20
DC characteristics 6-1
default download mode 2-60
destination
address 5-24
I/O-memory enable (DIOM) 4-63
detected parity error (from slave) (DPE) 4-5
device
ID (DID[15:0]) 4-3
select 3-8
specific initialization (DSI) 4-19
DEVSEL/ 3-8
timing (DT[1:0]) 4-5