Avago Technologies LSI53C1000R - Manual (Page 206)

4-94 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
DMA Next Address 64 (DNAD64) to provide 40-bit
addressing capability. This bit only functions if the
EN64TIBMV bit is set.
Index Mode 0 (64TIMOD clear) table entry format:
Index Mode 1 (64TIMOD set) table entry format:
EN64TIBMV Enable 64-Bit Table Indirect BMOV 1
Setting this bit enables 64-bit addressing for Table Indirect
BMOVs using the upper byte (bits [31:24]) of the first Dword
of the table entry. When this bit is cleared, Table Indirect
BMOVs use the
Static Block Move Selector (SBMS)
register to obtain the upper 32 bits of the data address.
EN64DBMV Enable 64-Bit Direct BMOV 0
Setting this bit enables the 64-bit version of a direct
BMOV. When this bit is cleared, direct BMOVs use the
Static Block Move Selector (SBMS) register to obtain the
upper 32 bits of the data address.
Registers: 0x58–0x59
SCSI Bus Data Lines (SBDL)
Read Only
SBDL SCSI Bus Data Lines [15:0]
This register contains the SCSI data bus status. Even
though the SCSI data bus is active LOW, these bits are
active HIGH. The signal status is not latched and is a true
representation of exactly what is on the data bus at the
time the register is read. This register is used when
[31:29] [28:24] [23:0]
Reserved Sel Index Byte Count
Source/Destination Address [31:0]
[31:24] [23:0]
Src/Dest Addr [39:32] Byte Count
Source/Destination Address [31:0]
15 0
SBDL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0