Avago Technologies LSI53C1000R - Manual (Page 385)

Index IX-13
SIP 2-50 , 2-51
SIST0 2-47
SIST1 2-47
slow memory
read cycle 6-56
write cycle 6-58
slow ROM pin 3-18
SODL
least significant byte full (OLF) 4-42
most significant byte full (OLF1) 4-44
SODL register 2-57
software reset (SRST) 4-47
source
I/O-memory enable (SIOM) 4-63
special cycle command 2-5
SREQ 2-51
stacked interrupts 2-50
start
address 5-13 , 5-14 , 5-22
DMA operation (STD) 4-68
sequence (START) 4-24
static block move selector (SBMS) 4-99
STOP command 2-10
stop signal 3-8
STOP/ 3-8
store instruction 2-32
stress ratings 6-2
subsystem ID 2-61
(SID[15:0]) 4-13
subsystem vendor ID 2-61
(SVID[15:0]) 4-12
SURElink 1-5
SWIDE register 2-57
SYNC_IRQD (SI) 4-50
synchronous
clock conversion factor (SCF[2:0]) 4-31
data transfer rates 2-41
operation 2-41
period, See transfer period
SCSI receive
2-39
SCSI send 2-38
transfer rate 2-45
system
application 1-3
system error 3-9
system signals 3-5
T
table indirect 5-6 , 5-20
index mode mapping 5-9
mode 5-19
table relative 5-20
target
asynchronous receive 6-64
asynchronous send 6-63
mode 5-10 , 5-15
SATN/ active (M/A) 4-73
mode (TRG) 4-26
ready 3-7
synchronous transfer 6-66 , 6-69
timing 6-15
TCK_CHIP 3-15
TDI_CHIP 3-15
TDO_CHIP 3-15
TEMP register 5-37
temporary (TEMP) 4-55
termination 2-39
test clock 3-15
test data in 3-15
test data out 3-15
test halt SCSI clock 3-15
test interface signals 3-15
test mode select 3-15
test reset 3-15
TEST_HSC 3-15
TEST_RST/ 3-15
third dword 5-14 , 5-33 , 5-37
timer test mode (TTM) 4-88
timing diagrams 6-14
TMS_CHIP 3-15
TolerANT 1-6
enable (TE) 4-87
technology 1-6
benefits 1-6
totem pole output 3-2
transfer
control 2-32
control instructions 5-27
and SCRIPTS instruction prefetching 2-32
count 5-35
counter 5-13
information 2-18
period factor 2-24
rate synchronous 2-41
width exponent 2-24
TRDY/ 2-10 , 3-7
U
Ultra SCSI
single-ended transfers 6-65 , 6-67
Ultra160 SCSI
benefits 1-4
designing an Ultra160 SCSI system 2-22
enabling 2-26
transfers 6-69