Script fetch selector (sfs), Memory move write selector (mmws), Registers: 0xa4–0xa7 – Avago Technologies LSI53C1000R User Manual
Page 210: Registers: 0xa8–0xab
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Registers
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0xA4–0xA7
Memory Move Write Selector (MMWS)
Read/Write
MMWS
Memory Move Write Selector
[31:0]
This register supplies AD[63:32] during data write
operations during Memory-to-Memory Moves and
absolute address STORE operations.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, the
MMWS register returns bits [31:0] of the SCRIPT RAM
PCI
Base Address Register Four (BAR4) (SCRIPTS RAM)
in bits [31:0] of the MMWS register when read. In this
mode, writes to the MMWS register affect no change.
Clearing the PCI Configuration Info Enable bit causes the
MMWS register to return to normal operation.
Registers: 0xA8–0xAB
SCRIPT Fetch Selector (SFS)
Read/Write
SFS
SCRIPT Fetch Selector
[31:0]
This register supplies AD[63:32] during SCRIPT Fetches
and Indirect Fetches (excluding Table Indirect Fetches).
This register can be loaded automatically using a 64-bit
jump instruction.
A special mode of this register can be enabled by setting
the PCI Configuration Info Enable bit in the
register. If this bit is set, bits
[23:16] of this register return the PCI
register value and bits [15:0] return the PCI
register value when read.
31
0
MMWS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
0
SFS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0