Avago Technologies LSI53C1000R - Manual (Page 345)

SCSI Timing Diagrams 6-63
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.36 Initiator Asynchronous Receive
Figure 6.37 Target Asynchronous Send
Table 6.40 Initiator Asynchronous Receive
Symbol Parameter Min Max Unit
t
1
SACK/ asserted from SREQ/ asserted 5 – ns
t
2
SACK/ deasserted from SREQ/ deasserted 5 – ns
t
3
Data setup to SREQ/ asserted 0 – ns
t
4
Data hold from SACK/ asserted 0 – ns
Valid n Valid n + 1
n + 1
n + 1
n
n
t
1
t
2
t
3 t
4
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/
Table 6.41 Target Asynchronous Send
Symbol Parameter Min Max Unit
t
1
SREQ/ deasserted from SACK/ asserted 5 – ns
t
2
SREQ/ asserted from SACK/ deasserted 5 – ns
t
3
Data setup to SREQ/ asserted 55 – ns
t
4
Data hold from SACK/ asserted 0 – ns
Valid n Valid n + 1
n + 1
n + 1
n
n
t
1
t
2
t
3
t
4
SREQ/
SACK/
SD[15:0]/,
SDP[1:0]/