Scsi control four (scntl4), Register: 0xbc – Avago Technologies LSI53C1000R User Manual

Page 213

SCSI Registers

4-101

Version 2.2

Register: 0xBC

SCSI Control Four (SCNTL4)
Read/Write

This register is automatically loaded when a Table Indirect Select or
Reselect SCRIPTS instruction is executed.

U3EN

Ultra160 Transfer Enable

Setting this bit enables Ultra160 transfers. This bit forces
all SCSI Block Move SCRIPTS instructions for ST Data-In
or ST Data-Out phases to become DT Data-In or DT
Data-Out phases.

AIPCKEN

AIP Checking Enable

Setting this bit enables the AIP (Asynchronous
Information Protection) checking of the upper byte lane of
protection information during Command, Status, and
Message phases. By default, AIP codes are generated
on the SCSI bus during all asynchronous transfers. To
disable this feature set bit 3, the Disable AIP Code
Generation bit, in

AIP Control One (AIPCNTL1)

Reserved

[5:4]

XCLKH_DT

Extra Clock of Data Hold on DT Transfer Edge

Setting this bit adds a clock of data hold to synchronous
DT SCSI transfers on the DT edge. This bit only impacts
DT transfers as it affects data hold to the DT edge.
Setting this bit reduces the synchronous transfer send
rate but does not reduce the transfer rate at which the
LSI53C1000R can receive inbound REQs, ACKs or data.
Refer to

Table 4.4

and

Table 4.5

for a summary of

available transfer rates and to

Figure 4.1

through

Figure 4.3

for examples of how the XCLKH bits function.

Note:

This bit does not affect CRC timings.

U3EN