Avago Technologies LSI53C1000R - Manual (Page 313)

PCI and External Memory Interface Timing Diagrams 6-31
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.20 Back to Back Write, 32-Bit Address and Data
t
9
t
4
t
3
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C1000R)
GPIO1_MASTER/
(Driven by LSI53C1000R)
REQ/
(Driven by LSI53C1000R)
PAR
(Driven by LSI53C1000R-
IRDY/
(Driven by LSI53C1000R)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
t
6
t
3
AD[31:0]
(Driven by LSI53C1000R-
C_BE[3:0]/
(Driven by LSI53C1000R)
t
3
CMD
t
2
REQ64/
(Driven by LSI53C1000R)
ACK64/
(Driven by LSI53C1000R)
t
10
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C1000R)
t
5
Addr
Out
Addr
Out
CMD
t
3
Addr; Target-Data)
Addr; Target-Data)
t
3
BE BE
Data
Out
t
3
t
3
t
3
Data
Out