Avago Technologies LSI53C1000R - Manual (Page 63)

SCSI Functional Description 2-33
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Note: This feature is only useful if Prefetching is disabled.
This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, burst opcode fetching is not necessary
when fetching instructions from SCRIPTS RAM.
2.2.8 Load and Store Instructions
The LSI53C1000R supports the Load and Store instruction type, which
simplifies data movement between memory and the internal registers. It
also enables the chip to transfer bytes to addresses relative to the
Data Structure Address (DSA) register. Load/Store data transfers to or
from the SCRIPTS RAM remain internal to the chip and do not generate
PCI bus cycles. While a Load/Store to or from SCRIPTS RAM is
occurring, any external PCI slave cycles that occur are retried on the PCI
bus. Setting the DISRC (Disable Internal SCRIPTS RAM Cycles) bit in
the
Chip Control Zero (CCNTL0) register disables this feature. For more
information on the Load and Store instructions, refer to
Chapter 5, “SCSI SCRIPTS Instruction Set.”
2.2.9 JTAG Boundary Scan Testing
With one exception, the LSI53C1000R includes support for JTAG
boundary scan testing in accordance with the IEEE 1149.1 specification.
The exception concerns the TST_RSTN pin. This pin must not be
toggled because it resets the JTAG TAP controller. For more information,
refer to the Boundary Scan Descriptor Language (BSDL) file.
This device accepts all required boundary scan instructions including the
optional CLAMP, HIGH-Z, and IDCODE instructions. The optional JTAG
pin TRST is not implemented. Reset of the JTAG logic through the TAP
controller occurs when TMS is held HIGH for at least 5 TCK clock cycles.
The LSI53C1000R uses an 8-bit instruction register to support all
boundary scan instructions. The data registers included in the device are
the Boundary Data register, the IDCODE register, and the Bypass
register. This device can handle a 20 MHz TCK frequency with all TAP
pins having a 50% duty cycle.