Avago Technologies LSI53C1000R - Manual (Page 299)

PCI and External Memory Interface Timing Diagrams 6-17
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.12 PCI Configuration Register Write
Table 6.18 PCI Configuration Register Write
Symbol Parameter
66 MHz PCI 33 MHz PCI
Unit Min Max Min Max
t
1
Shared signal input setup time 3 – 7 – ns
t
2
Shared signal input hold time 0 – 0 – ns
t
3
CLK to shared signal output valid 2 6 2 11 ns
Data In
Byte Enable CMD
t
2
t
1
t
2
t
1
t
2
t
1
t
1
t
2
t
2
t
3
t
2
t
1
t
3
t
2
t
1
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C1000R)
STOP/
(Driven by LSI53C1000R)
DEVSEL/
(Driven by LSI53C1000R)
IDSEL
(Driven by Master)
t
1
t
2
Addr In