Avago Technologies LSI53C1000R - Manual (Page 156)

4-44 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
C_D SCSI C_D/ Signal 1
This SCSI phase status bit is latched on the asserting
edge of SREQ/ when operating in either the initiator or
target mode. This bit is set when the corresponding
signal is active. This bit is useful when operating in the
low-level mode.
I_O SCSI I_O/ Signal 0
This SCSI phase status bit is latched on the asserting
edge of SREQ/ when operating in either the initiator or
target mode. This bit is set when the corresponding
signal is active. This bit is useful when operating in the
low-level mode.
Register: 0x0F
SCSI Status Two (SSTAT2)
Read Only
ILF1 SIDL Most Significant Byte Full 7
This bit is set when the most significant byte in the SCSI
Input Data Latch (SIDL) contains data. Data is transferred
from the SCSI bus to the SCSI Input Data Latch register
before being sent to the DMA FIFO. The data is then sent
to the host bus. The SIDL register contains SCSI data
received asynchronously. Synchronous data received
does not flow through this register.
R Reserved 6
OLF1 SODL Most Significant Byte Full 5
This bit is set when the most significant byte in the
SCSI Output Data Latch (SODL) contains data. The
SODL register is the interface between the DMA logic
and the SCSI bus for asynchronous send operations. In
the asynchronous mode, data is transferred from the host
bus to the
SCSI Output Data Latch (SODL) register, and
then to the SCSI bus. This bit can determine how many
bytes reside in the device when an error occurs.
7 6 5 4 3 2 1 0
ILF1 R OLF1 R SPL1 R LDSC SDP1
0 0 0 0 x 0 1 x